Radio transceiver comprising an arrangement for compensating for a DC component

ABSTRACT

A radio transceiver including a counter for outputting a DC compensation signal, an amplifier for receiving a input signal having a DC component and for receiving the DC compensation signal and forming a signal difference between the input signal and the DC compensation signal and a comparator for comparing the signal difference and a reference signal. The counter increases and decreases the DC compensation signal based on the output of the comparator such that the incrementation or decrementation of the counter is based on the DC component of the signal difference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to an electrical device, more specifically, aradio transceiver comprising an arrangement for compensating for a DCcomponent in an input signal to be processed, the compensatingarrangement comprising means for forming the signal difference betweenthe input signal and a DC compensation signal depending on a DCcomponent found.

2. Discussion of the Related Art

When AC signals are processed, for example, in audio amplifiers, radioreceivers and the like, the AC signal is processed in stages. Todetermine a specific DC operating point, the AC signal is converted in aprocessing stage to a specific DC level. For example, couplingcapacitors or coupling transformers which pass only the AC component tothe following stage are inserted between the processing stages.

Coupling capacitors and coupling transformers have a specific sizeespecially when used with low frequencies. While circuit arrangementscomprising resisters, diodes, transistors and so on can easily beintegrated in large numbers in integrated circuits, the volume of acoupling capacitor having a large capacitance prevents cost-effectiveintegration. Such coupling capacitors are therefore to be provided asexternal components outside the integrated circuit. This increases thecost of the modules, the cost of the components of the modules and thesize of the modules. A further detrimental effect of coupling capacitorshaving a large capacitance as they are necessary, for example, in mobileradio receivers for baseband processing of time multiplex signals(capacitances in the μF range) is that circuits comprising such largecapacitors cannot be simply turned off after a receive burst of about570 μsec in length to save battery capacity during the receive pauses ofabout 4 msec. As a result of the large turn-on and turn-off timeconstants, the circuit would not be able to adjust to the new receiveburst sufficiently fast. Thus the baseband circuit would have to remainturned on continuously, which reduces the operating time of the battery.

In integrated circuits the individual processing stages are normally DCcoupled. This means that a DC component of the input signal to beprocessed (for example, from a baseband mixer) either reduces the usefuldynamic range of the circuit, or even brings the circuit to saturation,so that no function can be executed any more.

For example, from the data sheet of the integrated circuit AD 7002,which sets out the baseband processing for the transmit and receivepaths of a GSM radio telephone; a DC compensation arrangement componentcomprising a digital offset register is known to compensate for an inputvoltage offset. A DC value measured during a calibration cycle is storedseparately for each filter input of the IC in the digital offsetregister. The value of the DC component stored in the correspondingregister is subtracted from the corresponding filter output signalduring a cycle of normal operation. This measurement is to be repeatedat least when the integrated circuit is initially used and, if afluctuation of the DC component cannot be excluded, for example, as aresult of temperature influences, at regular intervals. For ameasurement during the calibration cycle, however, the input signalcannot be used, so that only the DC component is measured which isavailable even if there is no input signal. Neither is it possible touse the IC during the calibration operation.

SUMMARY OF THE INVENTION

It is an object of the invention to provide a device of the type definedin the opening paragraph in which a compensation is effected for the DCcomponent contained in the input signal even when the device is inoperation without any effect on the function of the device. In addition,the arrangement for compensating for the DC component is to be suitableboth for discrete and for integrated structures.

In a device of the type defined in the opening paragraph this object isachieved in that the arrangement for compensating for the DC componentcomprises a counting device whose count direction is determined by theDC component found.

By subtracting the DC compensation signal from the input signal, the DClevel can be set irrespective of the input DC level. The advantage ofthe circuit arrangement is then that the means for forming the signaldifference can be arranged for measuring the DC component and forgenerating the DC compensation signal and have components that areeasily integrable. The continuous measurement of the DC component in theinput signal and the continuous formation of the DC compensation signalprovide that the measured DC component is continuously eliminated whilethe device is in operation. The counting device is furthermoreadvantageous in that it can be designed to have no passive storagecomponents such as, for example, capacitors. The counting speed of thecounting device and the counter length determine the smoothing timeconstant. As integrated counters are arranged such that, in theturned-off state, they retain the count for very long periods of time(of the order of 100 days), the counting operation can be continuedforthwith when the operating voltage is again applied to such a countingdevice. Therefore, such a circuit arrangement can particularly beapplied advantageously to radio transceivers operating in the time slotmode i.e. in which messages are exchanged in brief time slots. As thecorrection value is not lost even if the device is switched over orturned off, such an arrangement for compensating for the DC componentcan therefore be used particularly in multiplex or TDMA systems such asGSM. Furthermore, it is advantageous that the dynamic range of thesubsequent circuits i.e. of the circuits processing the DC compensatedsignal, is additionally extended considerably.

The DC compensation signal can be simply formed from the current countin that the arrangement for forming the DC compensation signal comprisesconverting means which are provided for converting the high-value countsof the counting device to a proportional analog value. For convertingthe count of the counting device to the DC compensation signal, thecount can be converted to an analog voltage value by a digital-to-analogconverter, for example.

The DC compensation signal can be easily smoothed in that thearrangement comprises smoothing means provided for smoothing ahigh-value output of the counting device. In an extremely simpleembodiment one of the high-value outputs of the counter is led to acapacitor. With an accordingly high-ohmic load of the capacitor and anaccordingly high counting speed of the counter, this integratingcapacitor needs to have only very little capacitance, as a result ofwhich this capacitor can also be integrated.

The useful life of the batteries present in the device, especially inhandhelds whose batteries have a limited service life depending on thesize of the handheld, may be extended in that the arrangement forcompensating for the DC component is structured in such a way that thevalue of the DC compensation signal, which value is available when aswitching signal for saving current is supplied, is retained in theturned-off state. Preferably, the arrangement for DC compensation is tobe designed such that when a switching signal for saving current occurs,the circuit can be rendered inoperative or be switched to a state inwhich the power consumption is very low. When the circuit is turned onagain, means are to be available that set the DC compensation signal toa value it had at the instant the circuit was turned off. One of thesemeans is that when the switching signal for saving current occurs, thecount is buffered and is set accordingly when the counting operation isresumed. Such an arrangement for DC compensation is especially suitablefor applications in which the operating time of the electrical device isinterrupted by pauses in which several circuit components are turned offfor the purpose of saving current. If a coupling capacitor is used,there would be the problem that the coupling capacitor would dischargewithin the pause intervals. If a coupling capacitor having a ratherlarge capacitance is used for transmitting very low frequency signalcomponents, there would be adjusting times which would prevent theelectronics from being turned off.

If the counting device has means for interrupting the counting processby means of the switching signal for saving current, the DC compensationsignal can be simply stored during the turn-off intervals byinterrupting the counting process of the counting device.

If the arrangement for compensating for the PC component is provided atthe input of a digital signal processor stage, in radio transceivers thearrangement can reduce low frequency signal components when highfrequency signals are converted to the baseband domain. For DC isolationof such signals having a low limit frequency, a corresponding couplingcapacitor would otherwise have a very large capacitance. In contrast,with the proposed circuit arrangement, the limit frequency only dependson the clock frequency and on the maximum count possible. As integratedcounter stages for achieving a high maximum count need little space,contrary to the space required by a corresponding coupling capacitor,limit frequencies of below one Hertz can be achieved without any problemin this manner.

The DC component can be set exactly to a reference value in that acomparing circuit for comparing the signal difference with a referencevalue is provided to determine the DC component. A comparator comparingthe DC component with a reference value is highly suitable as acomparing circuit to measure the DC component. This makes it possible toset at the output of the DC compensation arrangement a DC operatingpoint exactly defined by the reference voltage, at which operating pointthe AC component of the signal is exactly symmetrical. In integratedcircuits this reference voltage preferably corresponds to the centralbias voltage with which all the stages are supplied.

For the AC voltage signal not to have any influence on the DCcompensation, the arrangement for compensating for the DC componentcomprises integration means for a time-division integration of thesignal difference. As a result, the measured DC component will besubjected to an averaging over time when the DC compensation signal isgenerated. The integration time is to be selected considerably longerthan the reciprocal value of the lowest frequency valid signalcomponents. Preferably, the means for time-division integration are tobe selected such that they can be integrated as they require littlespace. The counting device is provided as an integration means in apreferred embodiment.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will now be further described with reference to theembodiments shown in the drawing Figures, in which:

FIG. 1 gives a diagrammatic representation of a radio transceiver;

FIG. 2 gives a diagrammatic representation of the receiving section of aradio transceiver which comprises a current-saving circuit and a firstembodiment for an arrangement for compensating for the DC component;

FIG. 3 shows a time diagram with the signals of a current-savingcircuit; and

FIG. 4 shows a further embodiment for an arrangement for compensatingfor the DC component.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The embodiment shows a mobile radio set for time-division multipleaccess (TDMA) in which transmit and receive signals are transmitted andreceived respectively, time-compressed as data packets at differentinstants. For this purpose, a common antenna 1 suffices, which antennais connected via an antenna switch 2 either to a receiving section 3 ora transmitting section 4 of the radio transceiver. A control circuit 5is provided for controlling the antenna switch 2, the receiving section3 and the transmitting section 4. The received signal is processed inknown manner in that it is reproduced via a loudspeaker 6. Spokensignals are recorded by a microphone 7 and are also processed in knownmanner by the transmitting section 4.

Control circuit 5 comprises, more specifically, a controlling sectionfor generating turn-off signals. Individual subassemblies can beseparately brought to a current-saving state by means of the turn-offsignals. While, for example, the signal processing in the low-frequencyarea is to be continuously turned on during a radio conversation toguarantee continuous speech input and output, the high frequencytransmitting and receiving sections are to be capable of operating onlyduring their assigned time slots. In the time intervals lying betweenthe assigned time slots, the relevant transmitting and receivingsections can thus be brought to a state in which current is saved.

FIG. 2 shows the receive circuit of the radio transceiverdiagrammatically shown in FIG. 1. The input signal received via theantenna 10 is preselected in a band filter 11 and amplified in a HFamplifier 12. The amplified signal is applied to a HF mixer 13 whichalso receives a first mixing signal from a local oscillator 14 and inwhich mixer the signals are connected to a first intermediate frequency.The intermediate frequency signal filtered in an intermediate frequencyfilter 15 is subsequently converted to a baseband signal U_(B) in abaseband mixing stage 16 by means of a second mixing signal coming froma baseband oscillator 17. This baseband signal U_(B) forms the inputsignal of an arrangement 30 for compensating for the DC component.

Depending on the modulation method used on the transmitting side, thebaseband signal U_(B) may contain very-low-frequency signal componentswhich must not be disregarded for an equalization and decoding of thesignal. On the other hand, the baseband signal U_(B) also comprises a DCcomponent which would reduce the dynamic range in the subsequent digitalsignal processing in a digital signal processor 18. For this reason, thearrangement 30 for compensating for the DC component to be describedhereafter is inserted between the output of the baseband mixer 16 andthe input of the digital signal processor 18.

The arrangement 30 for DC compensation comprises a circuit 31 forforming a signal difference, the circuit being supplied on a first inputwith the baseband signal U_(B) and on a second input with a DCcompensation signal U_(K). The circuit for forming a signal difference,for example, an accordingly connected differential amplifier, forms thesignal difference U_(B) -U_(K) between the baseband signal U_(B) and theDC compensation signal U_(K). The difference signal U_(B) -U_(K) isapplied to the signal processor 18 and a to comparator 33 via a low-passfilter 32.

The voltage comparator 33 compares the filtered difference signal U_(B)-U_(K) with a reference value U_(ref). As will be described in detail,it is possible with the reference voltage U_(ref) to set the DCcomponent of the output signal U_(A) of the DC compensation arrangement30 exactly to the reference voltage U_(ref). The result of thecomparison by the voltage comparator 33 is applied to the countdirection input U/D of a counting device 34 arranged as anup/down-counter. A clock signal generated by a clock generator 35 isapplied to the clock input C1 of the counter 34. The counter 34 is abinary counter whose output signals correspond to the individual bits ofthe result of the counter. The most significant output signals of thecounter 34 are applied to a digital-to-analog converter 36.

The output of the voltage comparator 33 produces a binary signal bywhich the count direction U/D of the counter 34 is controlled in such away that if a difference signal U_(B) -U_(K) exceeds the referencevoltage U_(ref), an up-counting takes place. In this manner the count ofthe counter 34 is incremented and thus also the DC compensation signalU_(K) is increased if the difference signal lies above the referencevoltage U_(ref). If the signal difference U_(B) -U_(K) lies belowU_(ref), the reverse is true. The smoothing time constant which isobtained with this arrangement, depends on the bit length N of thecounter 34 and on the clock frequency T of the clock generator 35. Thesmoothing time constant is the result of the quotient of the maximumcount 2^(N-1) and of the clock frequency f.

The smoothing time constant is to be selected such that it exceeds theperiod duration of the low-frequency signal component in the inputsignal U_(B). On the other hand, according to the scanning theorem, theclock frequency of the clock generator 35 is to be twice as high as themaximum input frequency that is to be processed. The limit frequency ofthe low-pass filter 32 is to be selected accordingly. In GSM equipmentone has to start from, for example, a maximum usable frequency of about100 kHz of the baseband signal U_(B).

During the receive pauses between the time slots there is provided acurrent controller (PD Logic) 21 which is to set the individual circuitcomponents to a state of current-saving and generates the associatedcontrol signals PD1, PD2, PD3 and PD4. To explain the function of thecurrent controller 21, FIG. 3 shows the output signals of the currentcontroller 21 plotted against the received TDMA time slot. The firstcurrent-saving control signal PD1 controls the power consumption of theHF amplifier 12. Due to the adjusting times of the HF amplifier 12, thecurrent-saving signal is to be such that it again puts the HF amplifier12 in operation in accordance with the adjusting time of the HFamplifier 12 before the beginning of the associated time slot. At theend of the receive time slot the HF amplifier 12 can again be set to thestate of current saving. The current-saving control signals PD2 for thelocal oscillator 14 and PD3 for the baseband oscillator 17 take anaccordingly longer adjusting time of these oscillators into account. Thecurrent-saving control signal PD4 for the arrangement 30 for DCcompensation, on the other hand, does not need to take any adjustingtimes into consideration and resets the arrangement 30 for DCcompensation at the beginning of the time slot to be processed from thestate of current saving to the active state and, at the end of the timeslot to be received, from the active state to the state of currentsaving. The current-saving control signal PD4 is then led to a controlinput I (Inhibit) of the clock generator 35. When the current-savingcontrol signal PD4 is available, the generation of the clock T by theclock generator 35 is interrupted. An appropriate structure of thecounter 34 provides that the internal registers of the counter 34 retaintheir register states until a new clock signal arrives.

As the power consumption in integrated modules, especially the CMOSmodules, particularly depends on the clock frequency, the powerconsumption of the arrangement 30 for DC compensation is drasticallylowered in that the clock signal T is interrupted. Except for the clocksignal being turned off, no further measures for reducing the powerconsumption or for storing the DC compensation signal are necessary inthis manner.

FIG. 4 shows a very simple embodiment for the DC compensationarrangement 30. The receiver components shown in FIG. 2 have beenomitted. Instead of applying various high-value output signals of thecounter 34 to a digitizer, only a single one of the high-value outputsignals of the counter 34 is applied to the circuit 31 for forming thesignal difference. Only a single capacitor 37 inserted between groundand the output used of the counter 34 is arranged for smoothing the DCcompensation signal U_(K). In order to preclude an erroneous functionwhen the counter 34 presents an overflow, it is suitable under givenconditions not to use the most-significant output signal (MSB) of thecounter 34 to produce the DC compensation signal U_(K). With ahigh-ohmic load of the smoothing capacitor 37 its capacitance may beselected to be very small, so that this smoothing capacitor 37 alsoallows of integration. With this simple embodiment it is thus possibleto reduce the required space of a digitizer to the space required forthe smoothing capacitor 37.

We claim:
 1. A radio transceiver comprising an arrangement forcompensating for a DC component in an input signal to be processed, thecompensating arrangement comprising means for forming the signaldifference between the input signal and a DC compensation signaldepending on a DC component found, wherein the arrangement forcompensating for the DC component comprises a counting device whosecount direction is determined by the DC component found.
 2. The radiotransceiver as claimed in claim 1, wherein the arrangement for formingthe DC compensation signal comprises converting means used forconverting the high-value counts of the counting device to aproportional analog value.
 3. The radio transceiver as claimed in claim1, wherein the arrangement comprises smoothing means used for smoothinga high-value output signal of the counting device.
 4. The radiotransceiver as claimed in claim 1, wherein the arrangement forcompensating for the DC component is structured in such a way that thevalue of the DC compensation signal (U_(K)), which value occurs when acurrent-saving signal (PD4) is available, is retained in the turned-offstate.
 5. The radio transceiver as claimed in claim 1, wherein thecounting device comprises means for interrupting the counting process bya current-saving signal.
 6. The radio transceiver as claimed in claim 1,wherein the counting device has a clock input, in that a clock generatoris provided for generating a clock signal to be applied to the clockinput of the counting device and in that a current-saving signal is usedfor interrupting the generation of the clock.
 7. The radio transceiveras claimed in claim 1, wherein the radio transceiver operating in thetime-division multiple access mode (TDMA).
 8. The radio transceiver asclaimed in claim 1, wherein the arrangement for compensating for the DCcomponent is arranged at the input of a digital signal processor stage(18).
 9. The radio transceiver as claimed in claim 1, wherein acomparator means (33) for comparing the signal difference (U_(B) -U_(K))with a reference value (U_(ref)) is arranged for determining the DCcomponent.
 10. The radio transceiver as claimed in claim 1, wherein thearrangement (30) for compensating for the DC component comprisesintegration means (34,35) for the time-division integration of thesignal difference (U_(B) -U_(K)).
 11. A radio transceiver comprising:acounter for outputting a DC compensation signal; first means forreceiving a input signal including at least a DC component and forreceiving said DC compensation signal, said first means forming a signaldifference between the input signal and said DC compensation signal; acomparator for comparing said signal difference and a reference signal;wherein said counter, coupled to said comparator, increases anddecreases said DC compensation signal based on said output of saidcomparator and wherein said incrementation or decrementation of saidcounter is based on the DC component of said signal difference.
 12. Theradio transceiver as claimed in claim 11, wherein said reference signalis a DC voltage at least substantially equal to the voltage of said DCcomponent.
 13. The radio transceiver as claimed in claim 11, whereinsaid first means includes converting means, coupled to said counter, forconverting the high-value counts of the counter to a proportional analogvalue.
 14. The radio transceiver as claimed in claim 11, includingsmoothing means, coupled to said first means and said counter, forsmoothing the DC compensation signal outputted from the counter.
 15. Theradio transceiver as claimed in claim 11, wherein the value of the DCcompensation signal, said value occurring when a current-saving signalis available, is retained in the turned-off state.
 16. The radiotransceiver as claimed in claim 11, wherein the counter includes meansfor interrupting the counting process by a current-saving signal. 17.The radio transceiver as claimed in claim 11, wherein the counterincludes a clock input and a clock generator, and a current-savingsignal is used for interrupting the generation of the clock.
 18. Theradio transceiver as claimed in claim 11, and including an input stagefor receiving an RF input signal and outputting said input signal and adigital signal processor stage; wherein said signal difference is aninput to said digital signal processor stage.
 19. A handheld mobileradio set, said mobile radio set comprising:a transmitter; and areceiver, said receiver including a counter for outputting a DCcompensation signal, receiving means for receiving a input signalincluding at least a DC component and for receiving said DC compensationsignal, said receiving means forming a signal difference between theinput signal and said DC compensation signal, a comparator for comparingsaid signal difference and a reference signal; and wherein said counter,coupled to said comparator, increases and decreases said DC compensationsignal based on said output of said comparator whereby saidincrementation or decrementation of said counter is based on the DCcomponent of said signal difference.